1. Field of the Invention
The present invention relates to a PLL circuit used as a circuit for regenerating a clock synchronized to a digital signal, such as a baseband signal for digital television.
2. Description of the Related Art
New techniques for transmission and reception with digital data have been developed in recent years for wireless broadcasting, such as for television and radio, and digital television broadcasting via satellites, and in some parts of the country, ground wave digital television broadcasting have been put to practical use. When demodulating the digital data for digital television, it is necessary to perform the demodulation according to a clock that is synchronized to the digital data. Thus, a clock regeneration circuit for regenerating the clock included in the digital data is provided in the digital demodulation circuit. In general, this clock regeneration circuit is configured as a PLL circuit, which uses digital data as a reference signal, as shown in FIG. 3. Demodulating with a regenerated clock is not limited to digital television signals and is applicable to digital demodulation in general.
First, in FIG. 3, a VCXO (voltage-controlled crystal scillator) 1, in which an oscillation frequency is controlled on the basis of a control voltage, generates an scillating signal, and the oscillating signal is divided by a divider 2. Thereafter, a phase comparator 3 detects a phase difference between the reference signal and the divided output of the VCXO 1 and outputs a digital signal in accordance with the phase difference. The output data of the phase comparator 3 is smoothed by a loop filter 4, then fed to a PWM (pulse width modulation) circuit 5.
The PWM circuit 5 generates a PWM pulse in accordance with the output data of the loop filter 4. The PWM circuit 5 outputs a pulse having a xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d level ratio on the basis of the output data of the loop filter 4. The PWM pulse, which has a fixed frequency, has a ratio of the xe2x80x9cHxe2x80x9d level width and xe2x80x9cLxe2x80x9d level width, namely, the duty ratio, that changes in accordance with the input data. For example, if the output data of the loop filter 4 is large, the xe2x80x9cHxe2x80x9d level width of the PWM pulse widens and the duty ratio increases. Conversely, if the output data of the loop filter 4 is small, the xe2x80x9cHxe2x80x9d level width of the PWM pulse widens and the duty ratio decreases.
The PWM pulse is fed to a LPF (low-pass filter) 6, and the LPF 6 performs digital to analog conversion by removing the high-frequency components and smoothing the PWM pulse. When the duty ratio of the PWM pulse is high, the output level of the LPF 6 rises, and when the duty ratio of the PWM pulse is low, the output level of the LPF 6 lowers. The output signal of the LPF 6 is supplied to the VCXO 1, and he oscillation frequency of the VCXO 1 is controlled in accordance with the output signal of the LPF 6.
In the circuit of FIG. 3, the VCXO 1 is controlled on the basis of a phase error between the reference signal and the output of the VCXO 1 at the phase comparator 3. Thus, the PLL circuit is controlled so that the oscillation frequency of the VCXO 1 substantially matches the frequency of the reference signal.
Since the oscillation frequency is set at a high precision, the VCXO is used for the oscillator in the PLL circuit of FIG. 3. Since the VCXO requires a crystal oscillating element or a varicap diode, it was not desirable to integrate the circuit of FIG. 3. Furthermore, in satellite digital television, for example, since the transmission speed of the baseband differs according to country or region, it was necessary to change the oscillating element for every destination for the VXCO, for which the variable frequency range is narrow.
To solve the aforementioned shortcomings, it is possible to use a VCO (voltage-controlled oscillator) having a wide variable frequency range and to have this single VCO adapt to all destinations. However, the lockup time of the PLL increases since the variable frequency range of the VCO is wide, and the oscillation frequency of the VCO itself deviates due to variations in the manufacturing process, resulting in a problem where lockup of the PLL becomes impossible.
According to the present invention, an error of an oscillation frequency is detected, and the oscillation frequency is adjusted in accordance with the detected error. As a result, when the oscillation frequency is large, this permits rapid adjustments compared to adjustments based on phase differences.
Furthermore, by controlling the oscillation of a voltage-controlled oscillator through the addition of a signal based on phase error and a signal based on frequency error, both control systems can be easily combined. Additionally, an appropriate control can be performed by adjusting the weight of these control systems.